The present disclosure relates to the field of computing hardware, and specifically to hardware devices. Still more specifically, the present disclosure relates to a design structure for selectively controlling current level to hardware devices.
A Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC) may provide multiple Input/Output (I/O) current busses, which receive a voltage source from one or more power pins. That is, an FPGA/ASIC may include current banks, which take voltage source(s), converts this voltage into current, and supplies this current to one or more devices that are coupled to their respective I/O current busses.